The present invention relates to a semiconductor device and method of manufacturing the same and, more particularly, to a structure and method for manufacturing a complementary metal-oxide-semiconductor (CMOS) with a V-shape channel nMOSFET.
Scaling of gate length of metal-oxide-semiconductor field-effect transistors (MOSFETs) can enhance performance. However, it increases stand-by power of very-large-scale integration (VLSI). Therefore, power consumption is a serious problem for VLSI. MOSFETs with long channel gate length have low stand-by power, but performance is relatively poor.
Increasing of mobility of electrons or holes can enhance performance without increasing stand-by power. Mobility of electrons or holes depends on surface crystalline orientations in silicon. In a MOSFET with an n-type channel (nMOSFET), electrons are responsible for conduction. In a MOSFET with a p-type channel (pMOSFET), holes are responsible for conduction. It is desirable to build an nMOSFET in a (100) surface and pMOSFET in a (110) surface in order to obtain the maximum electron mobility for the nMOSFET and the maximum hole mobility for the pMOSFET.
However, it is difficult and/or expensive to manufacture substrates that have hybrid surface crystalline orientations.